Category: Uncategorized

Specification Define functionality, Performance, Power, Area, Technology, and design constraints. RTL Write synthesizable RTL code(Verilog/VHDL) to describe the digital design. Verification Simulate and verify the RTL using testbenches to ensure functional correctness. Synthesis Convert RTL to a gate-level netlist using a standard cell library, optimizing for PPA. Physical Design Implement the design as a physical…

Feature wire reg integer Type Net type Variable type Variable type Assignment Continous Procedural Procedural only Storage No Storage Stores value Stores vlaue Usage Connect modules/combinational logic Sequential & Combinational logic Loop counter Data Width can be vector can be vector Fixed 32 bit Synthesizable yes yes not used for Hardware