| Specification | Define functionality, Performance, Power, Area, Technology, and design constraints. |
| RTL | Write synthesizable RTL code(Verilog/VHDL) to describe the digital design. |
| Verification | Simulate and verify the RTL using testbenches to ensure functional correctness. |
| Synthesis | Convert RTL to a gate-level netlist using a standard cell library, optimizing for PPA. |
| Physical Design | Implement the design as a physical layout.(floor ->place->CTS->Route). |
| Sign-Off | Ensure the design meets all physical and timing rules for tape-out. |
| Tape-Out | Generate GDSII layout file and deliver to the foundry. |
| Fabrication | Foundry manufactures the chip. |
| Test & Packing | Chips are tested (wafer sort, final test) and packaged for use. |
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